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Lattice Semiconductor
CSIX Level 1 IP Core User’s Guide
Functional Simulation under ModelSim (PC Platform)
Note: The following procedures are shown using the ORCA ? Series 4 version of the CSIX-to-PI40 core. For other
device versions, refer to the Readme release notes included in that evaluation package.
The RTL simulation environment contains a testbench and a simple application that uses the CSIX Level 1 IP core.
The application consists of the Generic FIFO Bridge loopback function. The application instantiates the IP core, a
Generic FIFO Bridge loopback module, and an ORCA SYSBUS module. The instantiated name of the application
is called “top”. The testbench includes a CSIX driver, a CSIX monitor, a Motorola Power PC driver, and an instanti-
ation of the “top” application. The CSIX driver sends 28 CSIX frames to the user application, based on the ?le:
~eval\testbench\vectors\vectors_32.v. The CSIX monitor inspects CSIX frames transmitted by the application and
dumps the results to a ?le called “cmon_out.dat” in the local simulation directory. The PowerPC driver gets its
instructions from the vectors_32.v ?le and dumps its results to a ?le called “mpu_out” in the local simulation direc-
tory. The following procedure describes the method for running a simulation of the user application.
A simulation script ?le is provided in the “eval” directory for RTL simulation. The script ?le eval_sim_csix2sine.do
uses precompiled models provided with this package. The pre-compiled library of models is located in the directory
eval\lib\modelsim\work .
Simulation Procedures
1. Launch ModelSim.
2. Using the main GUI, change the directory location.
Select: File_Change Directory_eval\simulation
3. Execute Simulation Macro
Select: Macro _ Execute Macro _ scripts\eval_sim_csix2sine.do
The pre-compiled model provided in this IP evaluation package does not work with the OEM version of ModelSim
embedded in the ispLEVER 3.0 software. For more information on how to use ModelSim, please refer to the Mod-
elSim User’s Manual.
Core Implementation
Lattice’s CSIX Level 1 evaluation package includes a simple CSIX user application to demonstrate the process of
synthesizing, mapping, and routing a design using the CSIX Level 1 IP core. The application consists of the basic
CSIX Level 1 IP core, a verilog module that loops the Generic FIFO Bridge output interface to the Generic FIFO
Bridge input interface, and a verilog module that instantiates the ORCA4 SYSBUS component, thereby providing a
Motorola Power PC interface to the core’s register interface. This example application is illustrated in Figure 10.
Once familiar with the core implementation process, the “real” application can replace the example application.
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相关PDF资料
CSIX-PI40-O4-N1 INTERFACE IP CSIX TO PI40 ORCA 4
CT0805S14BAUTOG VARISTOR 14VRMS 0805 SMD AUTO
CT1206K17G VARISTOR 17VRMS 1206 SMD
CTB-B-B-15 CIRCUIT BREAKER ROCKER 15A SP BK
CU3225K17AUTOG2 VARISTOR AUTO 17VRMS 3225 SMD
CU3225K250G2K1 VARISTOR STD 250VRMS 3225 SMD
CV10-RP-M-0 CONN JACK STR COAXIAL SMD
CVM50XM MEMBER MOD PIC12C508/PIC12C509
相关代理商/技术参数
CSIX-PI40-O4-N1 功能描述:输入/输出控制器接口集成电路 CSIX to PI40 RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray
CSJ-100 制造商:GREENLEE TOOL CO 功能描述:Digital Open Jaw Clampmeter 制造商:Greenlee Textron Inc 功能描述:CLAMPMETER
CSJ-23 功能描述:EXTRACTION TOOL FOR SCS RoHS:否 类别:工具 >> 插入，抽取 系列:* 标准包装:1 系列:* 其它名称:0011-03-00080011-03-0008-E00110300080011030008-E11-03-0008-E1103000811030008-EQ4729393AT0980176A
CSJ32C1 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32C3 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32C5 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32E1 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32E3 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals